1. Field of the Invention
The present invention relates to the field of logic circuits and more particularly a conversion circuit adapted to convert input signals corresponding to a first logic family into logic signals compatible with CMOS-type logic flip-flops.
2. Discussion of Background
For example, if it is desired to actuate CMOS logic flip-flops by logic signals issuing directly from a TTL type logic, given the variation range of the logic levels of a TTL logic, it is possible that the high and low logic levels be insufficiently differentiated to allow a reliable actuation of a CMOS logic. By way of numerical example, a CMOS logic circuit requires a threshold voltage of about 1.5 V while the TTL logic circuit has a voltage threshold of 1.4 V, which however can vary between 0.8 and 2 V in function of various parameters such as the fluctuations of power voltage, temperature variations, etc.
One particular object of the present invention is to produce such a conversion circuit which can operate at high speed, for example, at a frequency of about 10 MHz for a high level of 12 V, such a circuit being able, for example, to be used in actuating plasma panels. Another requirement for actuating plasma panels is to produce a circuit presenting a good immunity to interference or disturbing noise since, on the same integrated circuit chip as that comprising the CMOS logic, are located switching devices for the plasma panel switching voltages that can vary from 0 to more than 100 V, for example.
Among the circuits of the prior art intended to ensure a conversion between the logic signals of a first family and the logic signals for the CMOS flip-flop can be cited:
circuits in which the input occurs on the base of a PNP transistor; such circuits cannot be used to achieve the objects of the present invention due to the speed deficiency inherent in PNP transistors on silicon of which the maximal frequency is limited to values of about 1 to 4 MHz; PA1 circuits in which are placed at the input a CMOS inverter whose dimensions are disproportional; neither does this allow to achieve the speeds desired since the fact of using large-size MOS transistors means that said transistors have high disturbing capacities and thus that their operating speed is reduced; PA1 circuits that are wholly CMOS without bipolar transistors, do not allow, in a inherent manner, to overcome the difficulties associated to the creation of a sufficiently low voltage level for the CMOS flip-flop as lower threshold voltage. PA1 an input comparator comprising two NPN-type bipolar transistors connected by their emitters and receiving differential input signals on their bases; PA1 a CMOS flip-flop comprising two branches each of which is constituted by a P channel MOS transistor in series with two N channel MOS transistors, the gate of the second N channel MOS transistors of each branch being connected in order to set the current of these branches at the passing state while the gate of the first N channel MOS transistors of each branch are connected to the drains of the P channel transistors of the other branch and to an output terminal. PA1 the second branch of the comparator is connected to a V.sub.CC power voltage by a load constituted by a P channel MOS transistor, and to the gate of the P channel MOS transistor of the first branch of the flip-flop; PA1 the second branch of the CMOS flip-flop is connected to the V.sub.CC power voltage by a NPN bipolar transistor of which the base is connected to means for supplying a first potential taking one or other of the two values according to the state of the input and is also connected to the second branch of the comparator; and PA1 the gate of the P channel transistor of the second branch of the flip-flop is connected to means for supplying a second determined potential associated to the values of the first in order to ensure the conducting or the blocking of this transistor and thus of the state of the CMOS flip-flop. PA1 the means for supplying the first and second determined potentials comprise: a first series circuit constituted by a P channel MOS transistor, two NPN type bipolar transistors mounted in diodes and a current supply; PA1 the grids of the P channel MOS transistors of the first and second circuits in series are interconnected and are connected to the gate of the P channel transistor of the second branch of the comparator, these gates being connected to the drain of the P channel MOS transistor of the first circuit series or to a voltage point higher than that of this drain; PA1 the drain of the P channel transistor of the first series circuit is connected to the base of a PNP type bipolar transistors which is connected by its emitter to the base of the bipolar transistor of the second branch of the flip-flop and by its collector to the power voltage; PA1 a point of the first series circuit, having a voltage lower than 2 V.sub.BE (base to emitter) at the drain voltage of the P channel MOS transistor of this circuit, is connected to the gate of the P channel transistor of the second branch of the flip-flop.